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DATA SHEET
MOS INTEGRATED CIRCUIT
PD17215, 17216, 17217, 17218
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
DESCRIPTION
PD17215, 17216, 17217, 17218 (hereafter called PD17215 subseries) are 4-bit single-chip microcontrollers for
small general-purpose infrared remote control transmitters. It employs a 17K architecture of general-purpose register type devices for the CPU, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. Moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. In addition, a one-time PROM model, PD17P218, to which data can be written only once, is also available. It is convenient either for evaluating the PD17215 subseries programs or small-scale production of application systems. Detailed functions are described in the follwing manual. Be sure to read this manual when designing your system.
PD172xx Subseries User's Manual: IEU-1317
FEATURES
* Infrared remote controller carrier generator circuit (REM output) * 17K architecture: General-purpose register system * Program memory (ROM), Data memory (RAM)
PD17215
Program memory (ROM) 4 K bytes (2048 x 16) Data memory (RAM)
PD17216
8 K bytes (4096 x 16)
PD17217
12 K bytes (6144 x 16)
PD17218
16 K bytes (8192 x 16)
111 x 4 bits
223 x 4 bits
* 8-bit timer
:
1 channel
* Basic internal timer / Watchdog timer: 1 channel (WDOUT output) * Instruction execution time (can be changed in two steps) at fX 4 MHz at fX 8 MHz * External interrupt pin (INT) * I/O pins * Supply voltage : : : : : 4 s (high-speed mode)/8 s (ordinary mode) 2 s (high-speed mode)/4 s (ordinary mode) 1 20 VDD = 2.2 to 5.5 V (at fX = 4 MHz (high-speed mode)) VDD = 2.0 to 5.5 V (at fX = 4 MHz (ordinary mode)) * Low-voltage detector circuit (mask opation) Unless otherwise specified, the PD17215 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Document No. U12042EJ3V0DS00 (3rd edition) (Previous No. IC-3249) Date Published January 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1993
PD17215, 17216, 17217, 17218
APPLICATION
Preset remote controllers, toys, portable systems, etc.
ORDERING INFORMATION
Part Number Package 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic SOP (375 mil)
PD17215CT-xxx PD17215GT-xxx PD17216CT-xxx PD17216GT-xxx PD17217CT-xxx PD17217GT-xxx PD17218CT-xxx PD17218GT-xxx
Remark: xxx is ROM code number.
2
PD17215, 17216, 17217, 17218
PIN CONFIGURATION (TOP VIEW)
* 28-pin plastic SOP (375 mil)
PD17215GT-xxx, 17216GT-xxx, 17217GT-xxx, 17218GT-xxx
* 28-pin plastic shrink DIP (400 mil)
PD17215CT-xxx, 17216CT-xxx, 17217CT-xxx, 17218CT-xxx
P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 REM V DD X OUT X IN GND RESET WDOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P0D 1 P0D 0 P0C 3 P0C 2 P0C 1 P0C 0 P0B 3 P0B 2 P0B 1 P0B 0 P0A 3 P0A 2 P0A 1 P0A 0
GND INT
: Ground : External interrupt request signal input
P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input port (CMOS input) P0C0-P0C3 : Output port (N-ch open-drain output) P0D0-P0D3 : Output port (N-ch open-drain output) P0E0-P0E3 : I/O port (CMOS push-pull output) REM RESET VDD WDOUT XIN, XOUT : Remote controller output (CMOS push-pull output) : Reset input : Power supply : Hang-up/low voltage detection output (N-ch open-drain output) : Oscillator connection
3
PD17215, 17216, 17217, 17218
BLOCK DIAGRAM
P0A 0 P0A 1 P0A 2 P0A 3
P0A
RF ROM
PD17215, 17216 : 111 x 4 bits PD17217, 17218 : 223 x 4 bits
Remote Control Divider
REM
8-bit Timer
P0B 0 P0B 1 P0B 2 P0B 3
P0B
SYSTEM REG. Interrupt Controller ALU
INT
P0C 0 P0C 1 P0C 2 P0C 3
P0C ROM
PD17215 : 2048 PD17216 : 4096 PD17217 : 6144 PD17218 : 8192
x x x x 16 bits 16 bits 16 bits 16 bits
Instruction Decoder
P0D 0 P0D 1 P0D 2 P0D 3
P0D
RESET WDOUT Program Counter
P0E 0 P0E 1 P0E 2 P0E 3
P0E Stack (5 levels)
Power Supply Circuit CPU Clock
V DD GND
X IN Basic Interval/ Watchdog Timer OSC X OUT
4
PD17215, 17216, 17217, 17218
CONTENTS 1. PIN FUNCTIONS ..............................................................................................................................
1.1 1.2 1.3 1.4 Pin Function List ..................................................................................................................................... Input/Output Circuits ............................................................................................................................... Processing of Unused Pins ..................................................................................................................... Notes on Using INT and RESET Pins .....................................................................................................
7
7 8 9 9
2.
MEMORY SPACE .............................................................................................................................
2.1 2.2 2.3 2.4 2.5 Program Counter (PC) ............................................................................................................................ Program Memory (ROM) ........................................................................................................................ Stack ....................................................................................................................................................... Data Memory (RAM) ............................................................................................................................... Register File (RF) ...................................................................................................................................
10
10 10 12 14 21
3.
PORTS ..............................................................................................................................................
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Port 0A (P0A0-P0A3) ............................................................................................................................... Port 0B (P0B0-P0B3) ............................................................................................................................... Port 0C (P0C0-P0C3) .............................................................................................................................. Port 0D (P0D0-P0D3) .............................................................................................................................. Port 0E (P0E0-P0E3) ............................................................................................................................... INT Pin .................................................................................................................................................... Switching Bit I/O ..................................................................................................................................... Specifying Pull-up Sesistor Connection ...................................................................................................
24
24 24 24 24 24 25 26 27
4.
CLOCK GENERATOR CIRCUIT ......................................................................................................
4.1 Instruction Execution Time (CPU Clock) Selection .................................................................................
28
28
5.
8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT ........................
5.1 5.2 5.3 Configuration of 8-bit Timer (with modulo function) ................................................................................. Function of 8-bit Timer (with modulo function) ........................................................................................ Carrier Generator Circuit for Remote Controller ......................................................................................
29
29 31 32
6.
BASIC INTERVAL TIMER/WATCHDOG TIMER .............................................................................
6.1 6.2 6.3 Source Clock for Basic Interval Timer ..................................................................................................... Controlling Basic Interval Timer .............................................................................................................. Operation Timing for Watchdog Timer ....................................................................................................
36
36 36 38
7.
INTERRUPT FUNCTIONS ................................................................................................................
7.1 7.2 7.3 Interrupt Sources .................................................................................................................................... Hardware of Interrupt Control Circuit ...................................................................................................... Interrupt Sequence .................................................................................................................................
39
39 40 44
5
PD17215, 17216, 17217, 17218
8. STANDBY FUNCTIONS ...................................................................................................................
8.1 8.2 8.3 8.4 8.5 HALT Mode ............................................................................................................................................. HALT Instruction Execution Conditions ................................................................................................... STOP Mode ............................................................................................................................................ STOP Instruction Execution Conditions ................................................................................................... Releasing Standby Mode ........................................................................................................................
46
46 47 47 49 49
9.
RESET ..............................................................................................................................................
9.1 9.2 9.3 Reset by Reset Signal Input ................................................................................................................... Reset by Watchdog Timer (Connect RESET and WDOUT pins) ............................................................ Reset by Stack Pointer (Connect RESET and WDOUT pins) .................................................................
50
50 50 51
10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS) .......................
51
11. ASSEMBLER RESERVED WORDS ................................................................................................
11.1 11.2 Mask Option Directives ........................................................................................................................... Reserved Symbols ..................................................................................................................................
52
52 53
12. INSTRUCTION SET ..........................................................................................................................
12.1 12.2 12.3 12.4 Instruction Set Outline ............................................................................................................................ Legend .................................................................................................................................................... List of Instruction Sets ............................................................................................................................ Assembler (AS17K) Built-In Macro Instruction ........................................................................................
58
58 59 60 62
13. ELECTRICAL SPECIFICATIONS ....................................................................................................
63
14. CHARACTERISTIC WAVEFORMS (REFERENCE VALUE) ........................................................... 70
15. APPLICATION CIRCUIT EXAMPLE ................................................................................................
73
16. PACKAGE DRAWINGS ...................................................................................................................
74
17. RECOMMENDED SOLDERING CONDITIONS ............................................................................... APPENDIX A. DIFFERENCES AMONG PD17215, 17216, 17217, 17218 AND PD17P218 ............ APPENDIX B. FUNCTIONAL COMPARISON OF PD17215 SUBSERIES RELATED PRODUCTS ......
76
77
78
APPENDIX C. DEVELOPMENT TOOLS ...............................................................................................
79
6
PD17215, 17216, 17217, 17218
1.
1.1
PIN FUNCTIONS
Pin Function List
No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 Symbol P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 4-bit N-ch open-drain output port. Can be used for key source output of key matrix. Function 4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low, standby function is released. Input Output Form On Reset
4-bit CMOS input port with pull-up resistor. Can be used for key return input of key matrix. When at least one of these pins goes low,standby function is released. Input
4-bit N-ch open-drain output port. Can be used for key source output of key matrix.
N-ch Opendrain
Lowlevel output
N-ch Opendrain
Lowlevel output
4-bit input/output port. 4 5 6 7 P0E0 P0E1 P0E2 P0E3 Can be set in inputset in input or output mode in 1-bit units. In output mode, this port functions as a highcurrent CMOS output port. In input mode, function as CMOS input and can bespecified to connect pull-up resistor by program. CMOS pushpull Input
8
REM
Outputs transfer signal for infrared remotecontroller. Active-high output. System reset input. CPU can be reset when low-level signal is input to this pin. While low-level signal is input, oscillator circuit is
CMOS pusl-pll
Low-level output
13
RESET
stopped. Can be connected to pull-upresistor by mask option.
-
Input
9 12 3
VDD GND INT
Power supply Ground External interrupt request signal input Output detecting hang-up and drop in supply voltage.This pin
-
Input Highimpedance Low-level output at low voltage detection (Oscillation stops)
14
WDOUT
watchdog timer, when an overflow/underflow occurs in the stack, or when the supply voltage drops below a specified level (mask option). Connect this pin to the RESET pin.
Opendrain
11 10
XIN XOUT
Connects ceramic oscillator for system clock oscillation
-

outputs at low level either when an overflow occurs in the
N-ch
7
PD17215, 17216, 17217, 17218
1.2 Input/Output Circuits The equivalent input/output circuit for each PD17215 pin is shown below. (1) P0A, P0B
VDD
(4)
RESET
V DD
Input buffer
Mask option
(2)
P0C, P0D
Input buffer
data
Output latch
Schmitt trigger input with hysteresis characN-ch
teristics
(5) (3) P0E
VDD
INT
Input buffer
data Pull-up register VDD data Output latch P-ch P-ch
Schmitt trigger input with hysteresis characteristics
output disable
N-ch
(6)
REM
VDD
Selector Input buffer
data
P-ch
output disable
N-ch
(7)
WDOUT
data
N-ch
8
PD17215, 17216, 17217, 17218
1.3 Processing of Unused Pins Process the unused pins as follows:
Table 1-1 Processing of Unused Pins
Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 REM INT WDOUT Recommended Connection Connect to VDD Connect to VDD Connect to GND Connect to GND Input : Connect to VDD or GND Output : Open Open Connect to GND Connect to GND
1.4
Notes on Using INT and RESET Pins In addition to the functions shown in 1.1 PIN FUNCTIONS, the INT and RESET pins also have a function to set a test
mode (for IC testing) in which the internal operations of the PD17215 are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the PD17215 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the INT or RESET pin is too long, noise superimposed on the wiring line of the pin main cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. * Connect diode with low VF between VDD and INT/RESET pin
V DD
* Connect capacitor between VDD and INT/RESET pin
V DD
Diode with low V F INT, RESET
V DD
V DD
INT, RESET
If the test mode is set by the INT pin, low level is output from the WDOUT pin. In this case, connect the WDOUT and RESET pin.
9
PD17215, 17216, 17217, 17218
2.
2.1
MEMORY SPACE
Program Counter (PC) The program counter (PC) specifies an address of the program memory (ROM). The program counter is a 11/12/13-bit binary counter as shown in Fig. 2-1. Its contents are initialized to address 0000H at reset.
Fig. 2-1 Configuration of Program Counter
Page MSB PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0
PC (PD17215) PC (PD17216) PC (PD17217, 17218)
2.2
Program Memory (ROM) The configuration of the program memory is as follows:
Part Number
Capacity 2048 x 16 bits 4096 x 16 bits 6144 x 16 bits 8192 x 16 bits
Address 0000H-07FFH 0000H-0FFFH 0000H-17FFH 0000H-1FFFH
PD17215 PD17216 PD17217 PD17218
The program memory stores a program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Fig. 2-2 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH.
10
PD17215, 17216, 17217, 17218
Fig. 2-2 Program Memory Map
Address 0000H 0001H 0002H 0003H
16 bits Reset start address Basic interval timer interrupt vector External input (INT) interrupt vector 8-bit timer interrupt vtor ( PD17215) Subroutine entry Page 0 addresses for CALL addr instruction Branch addresses for BR addr instruction
Branch addresses for BR @AR instruction
07FFH 0FFFH ( PD17216) Page 1
Subroutine entry addresses for CALL @AR instruction
17FFH
( PD17217) ( PD17218)
Page 2
Page 3
Table reference addresses for MOVT DBR, @AR instruction
1FFFH
11
PD17215, 17216, 17217, 17218
2.3 Stack A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 Stack configuration
Fig. 2-3 shows the stack configurarion. A stack consists of a stack pointer (a 4-bit binary counter, the upper 1-bit fixed to 0), five 11-bit (PD17215)/12-bit (PD17216)/13-bit (PD17217, 17218) address stack registers, and three 5-bit (PD17215, 17216)/6-bit (PD17217, 17218) interrupt stack registers.
Fig. 2-3 Stack Configuration
Stack pointer (SP) b3 0 b2 b1 b0 0H 1H 2H 3H 4H 5H WDOUT pin goes low when the contents of the stack pinter are 6H-7H. 6H 7H b12 b11 b10 b9 b8
Address stack registers (ASR) b7 b6 b5 b4 b3 b2 b1 b0
SPb2 SPb1 SPb0
Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4 Undefined Undefined Undefined
PD17215 PD17216 PD17217, 17218
Interrupt stack registers (INTSK) b5 0H BANKSK0 1H 2H BANKSK1 BANKSK2 b4 BCDSK0 BCDSK1 BCDSK2 b3 CMPSK0 CMPSK1 CMPSK2 b2 CYSK0 CYSK1 CYSK2 b1 ZSK0 ZSK1 ZSK2 b0 IXESK0 IXESK1 IXESK2
PD17215, 17216 PD17217, 17218
12
PD17215, 17216, 17217, 17218
2.3.2 Function of stack
The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. The WDOUT pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is accepted. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur. 2.3.3 Stack Pointer (SP) and Interrupt Stack Pointer
Table 2-1 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H-07. Because there are only five stack registers available, however, the WDOUT pin goes low if the value of SP is 6 or greater.
Table 2-1 Operations of Stack Pointer
Instruction CALL addr CALL @AR MOVT DBF, @AR (1st Instruction Cycle) PUSH AR When Interrupt Is Accepted RET RETSK MOVT DBF, @AR (2nd Instruction Cycle) POP AR RET1 +1 +1 +1 0 -1 -1 -1 0 Value of Stack Pointer (SP) Counter of Interrupt Stack Register
13
PD17215, 17216, 17217, 17218
2.4 Data Memory (RAM) Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 2.4.1 Memory configuration
Figure 2-4 shows the configuration of the data memory (RAM). The data memory consists of two "banks": BANK0 and BANK1. In each bank, every 4 bits of data is assigned an address. The higher 3 bits of the address indicate a "row address" and the lower 4 bits of the address indicate a "column address". For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= a "nibble"). In addition, the data memory is divided into following six functional blocks: (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other nibbles, each bank has a system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory. The reset value is 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles long) of any bank of data memory. The row address of the general register is pointed by the general pointer (RP) in the system register (SYSREG). (4) Port register A port data register is resident on addresses 6FH, and 70H to 73H (5 nibbles) of BANK0 of data memory. No data can be written to the addresses 70H to 73H of BANK1 (the values of addresses 70H to 73H of BANK0 are read in this case).
PD17215 and 17216 are not provided with BANK1.
14
PD17215, 17216, 17217, 17218
(5) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. This memory area has a total of 223 nibbles (111 nibbles in BANK0 and 112 nibbles in BANK1).
PD17215 and 17216 are not provided with BANK1.
Fig. 2-4 Configuration of Data Memory
Column address 0 0 1 2 3 4 5 6 7 BANK 0 8 9 A B C D E F
Data buffer (DBF)
Row address
1 2 3 4 5 6 7 P0A P0B P0C P0D System register (SYSREG) P0E Example: Address 1AH in BANK 0
0
1
Column address 2 3 4 5
6
BANK 1 7 8
9
A
B
C
D
E
F
Row address
System register (SYSREG)
Caution:
No data can be written to the addresses 70H to 73H of BANK1 (the value of P0A to P0D are read in this case).
15
PD17215, 17216, 17217, 17218
2.4.2 System registers (SYSREG)
The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers: Address registers (AR0-AR3)* Window register (WR) Bank register (BANK)* Memory pointer enable flag (MPE) Memory pointers (MPH, MPL) Index registers (IXH, IXM, IXL) General register pointers (RPH, RPL) Program status word (PSWORD) *: The address register (AR3) and the bank register (BANK) are fixed to 0 in the PD17215 and 17216.
Fig. 2-5 Configuration of System Register
Address 74H 75H 76H 77H 78H 79H 7AH 7BH Index register (IX) Data memory row address pointer (MP) IXH MPH Bit IXM MPL IXL 7CH 7DH General register pointer (RP) 7EH 7FH Program status word (PSWORD)
Name
Address register (AR)
Window Bank register register (WR) (BANK)
Symbol
AR 3
AR 2
AR 1
AR 0
WR
BANK
RPH
RPL
PSW
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 (WR) (AR) ( PD17217, 17218) (AR) ( PD17216) (AR) ( PD17215) (IX) 000 * (RP)
Data
000 0000
(BANK) M 000 P000* *E (MP) *
BCC I CMY Z X DP E
00000 Initial Value At Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*: This bit is fixed to 0 in the PD17215 and 17216.
16
PD17215, 17216, 17217, 17218
2.4.3 General register (GR)
A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-6 shows the configuration of the general register. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. The row address is selected by the general register pointer (RP) of the system register. The RP having four significant bits in the PD17217 and 17218 can point to any row address in the range of 0H to 7H of each bank (BANK0 and BANK1). In the PD17215 and 17216, 3 bits are available in the RP. These bits can point to any row address in the range of 0H to 7H of BANK0. (2) Functions of the general register The general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. Similarly, the general register can be accessed by a Data Memory Manipulation instruction as it is a part of the data memory.
Fig. 2-6 Configuration of General Registers
General register pointer (RP) RPH RPL 0 1 A s s i g n e d t o 2 3 4 5 6 7 Port register BANK1 System registers RP
Port register
BANK0 0 1 2 3 4 5 6
Column address 7 8 9 A B C D E F
b 3 b 2 b 1 b 0 b3 b2 b1 b 0 F i x e d t o 0 F i x e d t o 0 F i x e d t o 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
General registers (16 nibbles)
Example: General registers when RP = 0000010B
General register settable range
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 B C1 D 2 f 3 l a4 g5 6 7 System registers Same system registers exist
17
PD17215, 17216, 17217, 17218
2.4.4 Data buffer (DBF)
The data buffer on the addresses 0CH to 0FH of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the Data Buffer The data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). Figure 2-7 shows the relationship between the data buffer and peripheral hardware.
Fig. 2-7 Data Buffer and Peripheral Hardware
Data buffer (DBF)
Peripheral address Internal bus 05H, 06H
Peripheral hardware 8-bit timer (TMC, TMM) Carrier generator for remote controller (NRZLTMM, NRZHTMM) Address register (AR)
03H, 04H
40H Program memory (ROM) Constant data
18
PD17215, 17216, 17217, 17218
Table 2-2 Relations between Hardware Peripherals and Data Buffer
Peripheral Register Transferring Data with Data Buffer Hardware Peripherals Name Symbol Peripheral Address 05H Data Buffer DBF0, DBF1 PUT/GET
8-bit counter 8-Bit Timer 8-bit modulo register NRZ low level period setting modulo register NRZ high level period setting modulo register
TMC
GET only
TMM
06H
DBF0, DBF1
PUT only
PUT GET NRZLTMM 03H DBF0, DBF1
Remote Controller Carrier Generator
NRZHTMM
04H
DBF0, DBF1
PUT (clear bit 3 of DBF1 to 0) GET (bits 3 of DBF1 is always 0)
Address Register
Address register
AR
40H
DBF0-DBF3
PUT (bits 0 to 3 of AR3 and bit 3 of 1 AR2 are any)* GET (bits 0 to 3 of AR3 and bit 3 of 2 AR2 are always 0)*
*1: In the PD17216: bits 0 to 3 of AR3 are any, in the PD17217, 17218: bits 1 to 3 of AR3 are any 2: In the PD17216: bits 0 to 3 of AR3 are always 0, in the PD17217, 17218: bits 1 to 3 of AR3 are always 0 (2) Table reference A MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF,@AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF).
Data buffer DBF 3 DBF 2 DBF 1 DBF 0
Program memory (ROM) MOVT DBF, @ AR
16 bits b15 b0
19
PD17215, 17216, 17217, 17218
(3) Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows: * When device operates Nothing changes even if data is written to the read-only register. If the unused address is read, an undefined value is read. Nothing changes even if data is written to that address. * Using assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. * If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur.
20
PD17215, 17216, 17217, 17218
2.5 Register File (RF) The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of AS17K, SETn, CLRn, and INITFLG. 2.5.1 Configuration of register file
Fig. 2-8 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging.
Fig. 2-8 Register File Access with PEEK or POKE Instructions
Column address 6 7 8 9
0 0 1 2 3 4 5 6 7
Row address
1
2
3
4
5
A
B
C
D
E
F
Data memory
POKE M063, WR
System register
0 1 2 POKE LCDMD, WR 3 Register file Control register PEEK WR, SP
21
PD17215, 17216, 17217, 17218
2.5.2 Control registers
The control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00H-3FH of the register file. Of these, however, only 14 nibbles are actually used. The remaining 50 nibbles are unused registers that are inhibited from being read or written. When the "PEEK WR, rf" instruction is executed, the contents of the register file addressed by "rf" are read to the window register. When the "POKE rf, WR" instruction is executed, the contents of the window register are written to the register file addressed by "rf". When using the assembler (AS17K), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Fig. 11-1 Register File List. SETn CLRn SKTn SKFn NOTn : Sets flag to "1" : Sets flag to "0" : Skips if all flags are "1" : Skips if all flags are "0" : Complements flag
INITFLG: Initializes flag 2.5.3 Notes on using register files
When using the register files, bear in mind the points described below. For details, refer to PD172xx subseries User's Manual (IEU-1317). (1) When manipulating control registers (read-only and unused registers) When manipulating the write-only (W), the read-only (R) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: * When device operates Nothing changes even if data is written to the read-only register. If the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. * Using assembler An error occurs if instruction is excecuted to read data to the write-only register. An error occurs if an instruction is executed to write data to the read-only register. An error also occurs if an instruction is executed to read or write the unused address. * When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if the write-only register is read, and an error does not occur. Nothing changes even if data is written to the read-only register, and an error does not occur. An undefined value is read if the unused address is read; nothing changes even if data is written to this address. An error does not occur.
22
PD17215, 17216, 17217, 17218
(2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand "rf" of the "PEEK WR, rf" or "POKE rf, WR" instruction if the 17K Series Assembler (AS17K) is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as the addresses 80H-BFH of BANK0. The portion of the register file overlapping the data memory (40H-7FH), however, can be defined as symbols as is.
23
PD17215, 17216, 17217, 17218
3.
3.1
PORTS
Port 0A (P0A0-P0A3) This is a 4-bit input port. Data is read through port register P0A (address 70H). This port is a CMOS input port with a
pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.2 Port 0B (P0B0-P0B3) This is a 4-bit input port. Data is read through port register P0B (address 71H). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. When a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.3 Port 0C (P0C0-P0C3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0C (address 72H). This port is an N-ch open-drain output port, and can be used as the key source of a key matrix. In the standby mode, this port outputs low-level signals. 3.4 Port 0D (P0D0-P0D3) This is a 4-bit output port. The contents of the output latch are read and output data is set through port register P0D (address 73H). This port is an N-ch open-drain output port, and can be used as the key source for a key matrix. In the standby mode, this port outputs low-level signals. 3.5 Port 0E (P0E0-P0E3) This is a 4-bit I/O port which can be set in either the input or output mode in 1-bit units by the P0EBIO (address 27H) of the register file. To read the input data or to set the output data, use the P0E register (address 6F). When data is read in the output mode, the contents of the output latch are read. Connection of a pull-up resistor can be specified in 1-bit units by the P0EBPU (address 17H) of the register file. (When the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) On reset, this port functions as an input port.
24
PD17215, 17216, 17217, 17218
3.6 INT Pin This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the IRQ flag (RF: address 3EH, bit 0) is set. The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to the pin, the INT flag is set to "1"; when the low level is input, the flag is reset to "0" (refer to 7.2.1 INT).
Fig. 3-1 Relations between Port Register and Each Pin
Contents to Be Read Bank Address Port Bit b3 P0A3 b2 P0A2 70H Port 0A b1 P0A1 b0 P0A0 Input only b3 P0B3 b2 P0B2 71H Port 0B b1 P0B1 b0 P0B0 b3 P0C3 b2 P0C2 0 72H Port 0C b1 P0C1 b0 P0C0 b3 P0D 3 b2 P0D 2 73H Port 0D b1 P0D 1 b0 P0D 0 b3 P0E3 b2 P0E2 6FH Port 0E b1 P0E1 b0 P0E0 COMS push-pull Pin status N-ch open-drain (Output only) Output latch Pin status Output Form Input Mode
Contents to Be Written Output Mode On Reset
Output Mode Input Mode
Input mode (w/pull-up resistor)
Output mode (Low level output) Output latch
Output latch
Input mode (w/pull-up resistor)
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PD17215, 17216, 17217, 17218
3.7 Switching Bit I/O The I/O which can be set in the input or output mode in bit units is called a bit I/O. P0E is a bit I/O port, which can be set in the input or output mode in bit units by the register file shown below. When the mode is changed from input to output, the P0E output latch contents are output to the port lines, as soon as the mode has been changed.
3 P0EBIO3
2 P0EBIO2
1 P0EBIO1
0 P0EBIO0
Address: RF : 27H
On reset: 0H
R/W: R/W
P0EBIO0 0 1
Sets P0E0 Input/Output Mode Sets P0E0 in input mode Sets P0E0 in output mode
P0EBIO1 0 1
Sets P0E1 Input/Output Mode Sets P0E1 in input mode Sets P0E1 in output mode
P0EBIO2 0 1
Sets P0E2 Input/Output Mode Sets P0E2 in input mode Sets P0E2 in output mode
P0EBIO3 0 1
Sets P0E3 Input/Output Mode Sets P0E3 in input mode Sets P0E3 in output mode
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PD17215, 17216, 17217, 17218
3.8 Specifying Pull-up Resistor Connection Whether or not a pull-up resistor is connected to port P0E can be specified by the following registers of the register file in 1-bit units when the port is in the input mode*.
3
2
1
0
Address: RF : 17H
On reset: 0H
R/W: R/W
P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0
P0EBPU0 Connects Pull-Up Resistor to P0E 0 0 1 Not connected Connected
P0EBPU1 Connects Pull-Up Resistor to P0E 1 0 1 Not connected Connected
P0EBPU2 Connects Pull-Up Resistor to P0E 2 0 1 Not connected Connected
P0EBPU3 Connects Pull-Up Resistor to P0E3 0 1 Not connected Connected
*:
To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register.
27
PD17215, 17216, 17217, 17218
4.
4.1
CLOCK GENERATOR CIRCUIT
Instruction Execution Time (CPU Clock) Selection The PD17215 is equipped with a clock oscillator circuit that supplies clocks to the CPU and hardware peri-pherals.
Instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by using the POKE instruction. Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed. When using the high-speed mode, pay attention to the supply voltage. (Refer to 13. ELECTRICAL SPECIFICATIONS.) At reset, the ordinary mode is set.
3 0
2 0
1 0
0 SYSCK
Address: RF : 02H
On reset: 0H
R/W: R/W
SYSCK 0 1
Selects Instruction Execution Time Ordinary mode 32/f X (8 s) High-speed mode 16/f X (4 s)
Figures in ( ): indicate figures when system clock f X= 4 MHz.
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PD17215, 17216, 17217, 17218
5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT
The PD17215 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 Configuration of 8-bit Timer (with modulo function) Figure 5-1 shows the configuration of the 8-bit timer. As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H, bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1) and TMCK0 (address 33H, bit 0) of the register file. The value of the 8-bit counter is read by using the GET instruction through DBF (data buffer). No value can be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value of the modulo register cannot be read. When the value of the counter coincides with that of the modulo register, an interrupt flag (IRQTM: address 3FH, bit 0) of the register file is set.
TMC
7 6 5 4 3 2 1 0 Address Peripheral register: 05H On reset 00H R/W R
8-bit counter
TMM
7 6 5 4 3 2 1 0 Address Peripheral register: 06H On reset FFH R/W W
8-bit modulo register
Caution:
Do note clear TMM to 0 (IRQTM is not set).
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PD17215, 17216, 17217, 17218
Fig. 5-1 Configuration of 8-bit Timer and Remote Controller Carrier Generator Circuit
Data buffer
Internal bus 8-bit timer
RF : 33H TMEN TMRES TMCK1 TMCK0
f X/32 f X /64 f X /256 Selector
8-bit modulo register TMM
Comparator
IRQTM
R S
Q 8-bit counter TMC
Remote controller carrier generator circuit f X /2 SW 7-bit counter RF : 11H Comparator bit 7 x 7-bit modulo register NRZLTMM NRZ NRZBF RF : 12H
7-bit counter
Comparator bit 7 0 fixed 7-bit modulo register NRZHTMM
REM
Remark: 30
TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers.
PD17215, 17216, 17217, 17218
5.2 Function of 8-bit Timer (with modulo function)
3 TMEN 2 TMRES 1 TMCK1 0 TMCK0 Address RF : 33H On reset 8H
*1
R/W R/W
*2
TMCK1 0 0 1 1
TMCK0 0 1 0 1
8-Bit Timer Clock Source Selection Count clock: fX/32 (Measurement time range: 8 s to 2.048 ms) Count clock: fX/64 (Measurement time range: 16 s to 4.096 ms) Count clock : fX/256 (Measurement time range: 64 s to 16.384 ms) Remote control carrier generation circuit output
Value indicated by parentheses is for when ( ): f SYS (system clock) = f X = 4MHz TMRES 0 1 8-Bit Timer Reset Flag Data read out is always "0" Resets 8-bit counter and IRQTM
TMEN 0 1
8-Bit Timer Count Enable Flag Stops 8-bit timer count operation Enable 8-bit timer count operation (falling edge)
*1: When the STOP mode is released, bit 3 must be set. 2: Bit 2 is a write-only bit.
NRZLTMM
7 x 6 5 4 3 2 1 0 Address Peripheral register: 03H On reset Undefined R/W R/W
7-bit modulo register
Bit 7 0 1
Output Control of REM Pin When NRZ = 1, carrier output to REM pin When NRZ = 1, high-level output to REM pin
NRZHTMM
7 0 6 5 4 3 2 1 0 Address Peripheral register: 04H On reset Undefined R/W R/W
7-bit modulo register
Bit 7 Fixed to 0
31
PD17215, 17216, 17217, 17218
5.3 Carrier Generator Circuit for Remote Controller
PD17215 is provided with a carrier generator circuit for the remote controller.
The remote controller carrier generator circuit consists of a 7-bit counter, NRZ high-level period setting modulo register (NRZHTMM), and NRZ low-level period setting modulo register (NRZLTMM). The high-level and low-level periods are set in the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency. The system clock (fx) is divided by two and is input to the 7-bit counter. Therefore, when a 4-MHz oscillator is used, 2 MHz (0.5 s) is input to the counter as the clock; when a 32-kHz oscillator (fXT) is used, 16 kHz is input. The NRZ high-level output period setting modulo register is called NRZHTMM, and the NRZ low-level period setting modulo register is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents for these register are read by the GET instruction. Bit 7 of NRZLTMM specifies whether the carrier or high level is output to the REM pin. To output the carrier, be sure to clear bit 7 to 0. 5.3.1 Remote controller signal output control
The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF for the register file and timer 0. While the NRZ content is "1", the clock generated by the remote controller carrier generator circuit is output to the REM pin; while the NRZ content is "0", the REM pin outputs a low level. The NRZBF content is automatically transferred to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes in synchronization with the timer 0 counting operation. If the interrupt signal is generated from timer 0 with the REM pin at the high level, NRZ being "1", and the carrier clock at the high level, the REM pin output is not in accordance with the updated content of NRZ, until the carrier clock goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). When the content of NRZ is "0", the remote controller carrier generator circuit stops. However, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the NRZ content becomes "0". An actual example showing a remote controller signal output to the REM pin is presented below. When bit 7 of NRZLTMM is 0 (carrier output)
NRZ
REM
MAX. 500 ns (delay)* (f x = 4 MHz)
REM pin does not go low until carrier goes low even if NRZ becomes 0
*: Value when (TMCK1, TMCK0) (1, 1). When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock.
32
PD17215, 17216, 17217, 17218
When bit 7 of NRZLTMM is 0 (carrier not output)
NRZ
REM
3 0
2 0
1 0
0 NRZ
Address RF : 12H
On reset 0H
R/W R/W
NRZ 0 1
NRZ Data Outputs low level to REM pin Outputs a carrier to REM pin or high level output
3 0
2 0
1 0
0 NRZBF
Address RF : 11H
On reset 0H
R/W R/W
NRZBF 0 1
NRZ Data Output Next NRZ buffer bit. Transfered to NRZ by interrupt signal for 8-bit timer.
Setting carrier frequency and duty factor Where the system clock frequency is fX and carrier frequency is fC: l (division ratio) = fX/(2 x fC) l is divided into m:n and is set in the modulo registers as follows: High-level period set value = {l x m/(m + n)} - 1 Low-level period set value = {l x n/(m + n)} - 1 Example: Where fc = 38 kHz, duty factor (high-level period) = 1/3, and fx = 4 MHz, l = 4 MHz/(2 x 38 kHz) = 52.6 m:n = 1:2 From the above, the value of the modulo register is: High-level period * * 17 = * 34 Low-level period = * Therefore, the carrier frequency is 37.74 kHz.
33
PD17215, 17216, 17217, 17218
Table 5-1 Carrier Frequency List (fx = 4 MHz)
Set value NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH tH (s) NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH 0.5 1.0 2.5 5.0 8.0 8.0 9.0 9.0 13.0 32.0 64.0 tL (s) 0.5 1.5 2.5 5.0 8.0 17.0 17.0 17.5 27.0 32.0 64.0 1/fC (s) 1.0 2.5 5.0 10.0 16.5 25.0 26.0 26.5 40.0 64.0 120.0 fC (kHz) 1000 400 200 100 60.6 40.0 38.5 37.7 25.0 15.6 7.8 Duty 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2
tH
tL
REM (fC) 1/fC
34
PD17215, 17216, 17217, 17218
5.3.2
Countermeasures against noise during transmission (carrier output)
When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several of equivalent resistance (r) exists in the power source as shown in Fig. 5-2. This resistance increases to 10 to 20 if the supply voltage drops to 2 V. While the carrier is output from the REM pin (while the infrared LED lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures: <1> Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. <2> Locate the oscillator as close as possible to the microcontroller and shield it with GND lines (as indicated by the shaded portion in the figure below). <3> Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. <4> To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. <5> To improve the reliability in case of program hang-up, use the watchdog timer (connect the WDOUT and RESET pins).
Fig. 5-2 Example of Countermeasures against Noise
0.5 - 1 A Infrared LED
REM
VDD Microcomputer r + - Batteries RESET WDOUT
VSS
Remarks
1: The INT and RESET pins are multiplexed with test pins (refer to 1.4 NOTES ON USING OF INT AND RESET PINS). 2: In this figure, the RESET pin is connected to a pull-up resistor by mask option.
35
PD17215, 17216, 17217, 17218
6. BASIC INTERVAL TIMER/WATCHDOG TIMER
The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 Source Clock for Basic Interval Timer The system clock (fx) is divided, to generate the source clock for the basic interval timer. The input clock frequency for the basic interval timer is fx/27. When the CPU is set in the STOP mode, the basic interval timer also stops. 6.2 Controlling Basic Interval Timer The basic interval timer is controlled by the bits on the register file. That is, the basic interval timer is reset by BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the watchdog timer is reset by WDTRES.
Fig. 6-1 Basic Interval Timer Configuration
fX /2 18 fX /2 20
System clock f X
1/2 7 divider
1/2 11 divider
1/2 divider
1/2 divider
1/2 divider
Selector B
WDOUT
BTMRES
WDTRES
BTMCK
IRQBTM
36
PD17215, 17216, 17217, 17218
3 WDTRES 2 BTMCK 1 BTMRES 0 0 Address RF : 03H On reset 0H R/W R/W*
BTMRES 0 1
Basic Interval Timer Reset Data read out is always "0" Writing "1" resets basic interval timer
BTMCK 0 1
Basic Interval Timer Mode Selection Generates interrupt signal IRQBTM every f X /2 20 Generates interrupt signal IRQBTM every f X /2 18
WDTRES 0 1
Watchdog Timer Reset Data read out is always "0" Writing "1" resets watchdog timer (f X /2 21 counter)
*:
Bits 1 and 3 are write-only bits.
37
PD17215, 17216, 17217, 17218
6.3 Operation Timing for Watchdog Timer The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed time*, it judges that "the program has hung up", and the PD17215 is reset. It is therefore necessary to reset through programming the watchdog timer with in a fixed time. The watchdog timer can be reset by setting WDTRES to 1. *: Fixed time: approx. 340 ms (at 4 MHz) Coutions 1: The watchdog timer cannot be reset in the shaded range in Fig. 6-2. Therefore, set WDTRES before both the fx/221 and fx/220 signals go high. 2: Refer to 9. RESET for the WDOUT pin function.
Fig. 6-2 Watchdog Timer Operation Timing
f X /218 f X /219 f X /220 f X /221 INTBTM (f X/2 20 ) INTBTM (f X/2 18 ) WDOUT Watchdog timer reset signal WDOUT output goes low if WDTRES is not set
WDTRES Setting WDTRES at this timing is invalid
38
PD17215, 17216, 17217, 17218
7.
7.1
INTERRUPT FUNCTIONS
Interrupt Sources
PD17217 is provided with three interrupt sources.
When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1.
Table 7-1 Vector Address
Priority 1 2 3 8-bit timer INT pin rising and falling edges Basic interval timer Interrupt Source Ext/Int Internal External Internal Vector Address 0003H 0002H 0001H
When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is accepted, the interrupt is disabled. To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions. Caution: In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing the saved contents be returned to thier original location.
39
PD17215, 17216, 17217, 17218
7.2 Hardware of Interrupt Control Circuit
This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts.
Table 7-2 Interrupt Request Flags and Interrupt Enable Flag
Interrupt Request Flag IRQTM IRQ IRQBTM Interrupt Enable Flag IPTM IP IPBTM
Signal Setting Interrupt Request Flag Reset by 8-bit timer. Set when edge of INT pin input signal is detected Reset by basic interval timer.
40
PD17215, 17216, 17217, 17218
7.2.1 INT
This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to "1"; when a low level is input, the flag is reset to "0".
3 0
2 0
1 0
0 INT
Address RF : 0FH
On reset Undefined
R/W R
INT 0 1
INT Pin Level Detection INT pin : Low level INT pin : High level
7.2.2
IEG
This pin selects the interrupt edge to be detected on the INT pin. When this flag is "0", the interrupt is detected at the rising edge; when it is "1", the interrupt is detected at the falling edge.
3 0 2 0 1 0 0 IEG Address RF : 1FH On reset 0H R/W R/W
IEG 0 1
INT Pin Interrupt Detection Edge Selection Rising edge of INT pin Falling edge of INT pin
41
PD17215, 17216, 17217, 17218
7.2.3 Interrupt enable flag
This flag enables each interrupt source. When this flag is "1", the corresponding interrupt is enabled; when it is "0", the interrupt is disabled.
3 0
2 IPBTM
1 IP
0 IPTM
Address RF : 2FH
On reset 0H
R/W R/W
IPTM 0 1
8-Bit Timer Interrupt Enable Flag Disables interrupt acceptance by 8-bit timer Enables interrupt acceptance by 8-bit timer
IP 0 1
INT Pin Interrupt Enable Flag Disables interrupt acceptance by INT pin input Enables interrupt acceptance by INT pin input
IPBTM 0 1
Basic Interval Timer Interrupt Enable Flag Disables interrupt acceptance by basic interval timer Enables interrupt acceptance by basic interval timer
42
PD17215, 17216, 17217, 17218
7.2.4 IRQ
This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to "1". When the interrupt has been accepted, the interrupt request flag is reset to "0". The interrupt request flag can be read or written by the program. Therefore, when it is set to "1", an interrupt can be generated by the software. By writing "0" to the flag, the interrupt pending status can be canceled.
3 0
2 0
1 0
0 IRQBTM
Address RF : 3DH
On reset 0H
R/W R/W
IRQBTM 0 1
Basic Interval Timer Interrupt Request Flag Interrupt request has not been made. Basic interval timer interrupt request has been made.
3 0
2 0
1 0
0 IRQ
Address RF : 3EH
On reset 0H
R/W R/W
IRQ 0 1
INT Pin Interrupt Request Flag Interrupt request has not been made. Interrupt request has been made at rising edge or falling edge of INT input.
3 0
2 0
1 0
0 IRQTM
Address RF : 3FH
On reset 1H*
R/W R/W
IRQTM 0 1
8-Bit Timer Interrupt Request Flag Interrupt request has not been made. 8-bit timer interrupt request has been made.
*: 1H is also set after releasing STOP mode.
43
PD17215, 17216, 17217, 17218
7.3 Interrupt Sequence If IRQxxx flag is set to "1" when IPxxx flag is "1", interrupt processing is started after the instruction cycle of the instruction executed when IRQxxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If IPxxx flag is "0", the interrupt processing is not performed even if IRQxxx flag is set, until IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 Operations when interrupt is accepted
When an interrupt has been accepted, the CPU performs processing in the following sequence:
Clears IRQxxx corresponding to INTE flag and accepted interrupt
Decrements value of stack pointer by 1 (SP-1)
Saves contents of program counter to stack addressed by stack pointer
Loads vector address to program counter
Save contents of PSWORD to interrupt stack register
One instruction cycle is required to perform the above processing.
44
PD17215, 17216, 17217, 17218
7.3.2 Returning from interrupt processing routine
To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle.
Loads contents of stack addressed by stack pointer to program counter
Loads contents of interrupt stack register to PSWORD
Increments value of stack pointer by 1
To enable an interrupt after the processing of an interrupt has been finished, the EI instruction must be executed immediately before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, the interrupt is not accepted between the EI and RETI instructions.
45
PD17215, 17216, 17217, 17218
8. STANDBY FUNCTIONS
PD17215 is provided with HALT and STOP modes as standby functions. By using the standby function, current
dissipation can be reduced. In the HALT mode, the program is not executed, but the system clock fx is not stopped. This mode is maintained, until the HALT mode release condition is satisfied. In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until the STOP mode release condition is satisfied. The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP instruction has been executed. 8.1 HALT Mode In this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current dissipation. Use the HALT instruction to set the HALT mode. The HALT mode releasing condition can be specified by the operand for the HALT instruction, as shown in Table 8-1. After the HALT mode has been released, the operation is performed as shown in Table 8-1 and Figure 8-2. Caution: Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the HALT 8H instruction; otherwise, the HALT mode may not be set.
Table 8-1 HALT Mode Releasing Conditions
Operand Value 0010B (02H) Releasing Conditions When interrupt request (IRQTM) occurs for 8-bit timer <1> When interrupt request (IRQTM, IRQWTM, or IRQ), whose interrupt enable flag (IPTM, IPBTM, or IP) is set, occurs <2> When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Inhibited
1000B (08H)
Other Than Above
Table 8-2 Operations After HALT Mode Release (1/2)
(a) HALT 08H
Interrupt Status Don't care Interrupt Enable Flag Don't care Disabled DI When Release Condition Is Satisfied by Interrupt EI Enabled Branches to interrupt vector address Enabled Disabled Instruction next to HALT is executed Standby mode is not released Operations after HALT Mode Release Instruction next to HALT is executed Standby mode is not released
HALT Mode Released by: Low-Level Input of P0A0-P0A3, P0B0-P0B3
46
PD17215, 17216, 17217, 17218
Table 8-2 Operations After HALT Mode Release (2/2)
(b) HALT 02H
Interrupt Status Interrupt Enable Flag Disabled DI Enabled 8-Bit Timer Disabled EI Enabled Branches to interrupt vector address Instructions are executed from the instruction next to the HALT instruction. Operations after HALT Mode Release
HALT Mode Released by:
8.2
HALT Instruction Execution Conditions The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to prevent the program
from hangup. If the conditions in Table 8-3 are not satisfied, the HALT instruction is treated as an NOP instruction.
Table 8-3 HALT Instruction Execution Conditions
Operand Value 0010B (02H) Execution Conditions When all interrupt request flags (IRQTM) of 8-bit timer are reset <1> When interrupt request flag is reset, corresponding to interrupt whose interrupt enable flag (IPTM, IPBTM, or IP) is set <2> When high level is input to all P0A0-P0A3 and P0B0-P0B3 pins Other Than Above Inhibited
1000B (08H)
8.3
STOP Mode In the STOP mode, the system clock (fx) oscillation is stopped and the program execution is stopped to minimize current
dissipation. To set the STOP mode, use the STOP instruction. The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4. After the STOP mode has released, the operation is performed as follows: <1> Resets IRQTM. <2> Starts the basic interval timer and watchdog timer (does not reset). <3> Resets and starts the 8-bit timer. <4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter coincides with the value of the modulo register (IRQTM is set).
47
PD17215, 17216, 17217, 17218
The PD17215 oscillator circuit is stopped, when the STOP instruction has been executed (i.e., in the STOP mode). Oscillation is not resumed, until the STOP mode is released. After the STOP mode has been released, the HALT mode is set. Set the time required to release the HALT mode by using the timer with modulo function. The time that elapses, after the STOP mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table.
8-Bit Modulo Register Set Value (TMM)
Time Required to Set Operation Mode after STOP Mode Release At 4 MHz
40H FFH
4.160 ms (64 s x 65) 16.384 ms (64 s x 256)
Remark: Caution:
Set the 8-bit modulo timer before executing STOP instruction. Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction; otherwise, the STOP mode may not be set.
Table 8-4 STOP Mode Releasing Conditions
Operand Value 1000B (08H) Others
Releasing Conditions When any of P0A0-P0A3 and P0B0-P0B3 pins goes low Inhibited
48
PD17215, 17216, 17217, 17218
8.4 STOP Instruction Execution Conditions The STOP instruction can be executed, only under special conditions, as shown in Table 8-5, to prevent the program from hangup. If the conditions in Table 8-5 are not satisfied, the STOP instruction is treated as an NOP instruction.
Table 8-5 STOP Instruction Execution Conditions
Operand Value 1000B (08H) Others
Execution Conditions High level input for all P0A0-P0A3 and P0B0-P0B3 pins Inhibited
8.5
Releasing Standby Mode Operations for releasing the STOP and HALT modes will be as shown in Fig. 8-1.
Fig. 8-1 Operations After Standby Mode Release
(a) Releasing STOP mode by interrupt
Wait (time set by TMM)
STOP instruction Stanby release signal Operation mode Oscillation
STOP mode Oscillation stops
HALT mode Oscillation
Operation mode
Clock
(b)
Releasing HALT mode by interrupt
HALT instruction
Stanby release signal Operation mode HALT mode Operation mode
Clock
Oscillation
Remark:
The dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted.
49
PD17215, 17216, 17217, 17218
9.
9.1
RESET
Reset by Reset Signal Input When a low-level signal more than 50 s is input to the RESET pin, PD17215 is reset. When the system is reset, the oscillator circuit remains in the HALT mode and then enters an operation mode, like when
the STOP mode has been released. The wait time, after the reset signal has been removed, is 16.384 ms (fx = 4 MHz). On power application, input the reset signal at least once because the internal circuitry operations are not stable. When
PD17215 is reset, the following initialization takes place:
(1) (2) (3) (4) (5) Program counter is reset to 0. Flags in the register file are initialized to their default values (for the default values, refer to Fig. 11-1 Register Files). The default value (0320H) is written to the data buffer (DBF). The hardware peripherals are initialized. The system clock (fx) stops oscillation.
When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 MHz) later.
Fig. 9-1 Reset Operation by RESET Input
Wait (about 16 ms at 4 MHz) RESET Operation mode or standby mode Starts from address 0H
HALT mode
Operation mode
Oscillation stops
9.2
Reset by Watchdog Timer (Connect RESET and WDOUT pins) When the watchdog timer operates during program execution, a low level is output to the WDOUT pin, and the program
counter is reset to 0. If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. Program so that the watchdog timer is reset at intervals of within 340 ms (at fx = 4 MHz) (set the WDTRES flag).
50
PD17215, 17216, 17217, 17218
9.3 Reset by Stack Pointer (Connect RESET and WDOUT pins) When the value of the stack pointer reaches 6H or 7H during program execution, a low level is output to the WDOUT pin, and the program counter is reset to 0. If the nesting level of the interrupt or subroutine call exceeds 5 (stack over flow), or if the return instruction is executed without correspondence between CALL and return (RET) instructions established, then regardless of a stack level of 0 (stack underflow), the program can be restarted from address 0H.
Table 9-1 Status of Each Hardware After Reset
RESET Input During Standby Mode 0000H Input/output Output latch Data Memory (RAM) General-purpose data memory (Except DBF, port register) DBF System register (SYSREG) WR Input 0 Retains previous status 0320H 0 Retains previous status RESET Input During Operation 0000H Input 0 Undefined
Hardware Program Counter (PC) Port
0320H 0 Undefined
Control Register 8-bit Timer Counter (TMC) Modulo register (TMM) Remote Controller Carrier Generator NRZ high level period setting modulo register (NRZHTMM) NRZ low level period setting modulo register (NRZLTMM) Basic Interval Timer/Watchdog Timer Counter
Refer to Fig. 11-1 Register Files 00H FFH Retains previous status 00H FFH Undefined
00H
00H
10. LOW-VOLTAGE DETECTOR CIRCUIT (CONNECT RESET AND WDOUT PINS)
The low-voltage detector circuit outputs a low level from the WDOUT pin for initialization (reset) to prevent program hangup that may take place when the batteries are replaced, if the circuit detects a low voltage. A drop in the supply voltage is detected if the status of TA = -10 to +85C, VDD = 0.8 to 2.2 V lasts for 1 ms or longer. Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. Although the voltage at which the the reset function is effected ranges from 0.8 to 2.2 V, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 8 to 32 s. Note that some oscillators stop oscillating before the reset function is effected. The low-voltage detector circuit can be set arbitrarily by the mask option.
51
PD17215, 17216, 17217, 17218
Caution: Connect a diode and a capacitor to the RESET pin as shown below to stabilize the operation.
Microcomputer VDD RESET WDOUT
Remark:
In this figure, the RESET pin is connected to a pull-up resistor by the mask option.
11. ASSEMBLER RESERVED WORDS
11.1 Mask Option Directives
When developing the PD17215 program, mask options must be specified by using mask option directives in the program. The RESET pin for PD17215 requires a mask option to be specified. 11.1.1 OPTION and ENDOP directives
That portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block. This block is described in the following format: Description: Symbol [Label: ] Mnemonic OPTION : : : ENDOP Operand Comment [;Comment]
11.1.2
Mask option definition directives
Table 19-1 lists the directives that can be used in the mask option definition block. Here is an example of mask option definition: Description format: Symbol field Mnemonic field OPTION OPTRES OPTPOC ENDOP PULLUP USEPOC ; RESET pin has pull-up resistors. ; Internal low-voltage detector circuit Operand field Comment field
52
PD17215, 17216, 17217, 17218
Table 11-1 Mask Option Definition Directives
Name Directive Operands 1st Operand Mask option of RESET PULLUP (w/pull-up resistor) OPEN (w/o pull-up resistor) USEPOC (low-voltage detector circuit provided) POC OPTPOC 1 NOUSEPOC (low-voltage detector circuit not provided) 2nd Operand 3rd Operand 4th Operand
RESET
OPTRES
1
11.2
Reserved Symbols
The symbols defined by the PD17215 device file are listed in Table 11-2. The defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 Register file
The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK and POKE instructions through the window register (WR). Fig. 11-1 shows the register file. 11.2.2 Registers and ports on data memory
The names of the registers assigned at addresses 00H through 7FH on the data memory and the names of ports assigned to address 70H and those that follow, and system register names are defined. Fig. 11-2 shows the data memory configuration. 11.2.3 Peripheral hardware
The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 11-3 shows the peripheral hardware.
53
PD17215, 17216, 17217, 17218
Table 11-2 Reserved Symbols (1/2)
Symbol Name DBF3 DBF2 DBF1 DBF0 AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.0CH 0.0DH 0.0EH 0.0FH 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 0.70H.0 0.70H.1 0.70H.2 0.70H.3 0.71H.0 0.71H.1 0.71H.2 0.71H.3 0.72H.0 0.72H.1 0.72H.2 0.72H.3 0.73H.0 0.73H.1 0.73H.2 0.73H.3 R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15-12 of data buffer Bits 11-8 of data buffer Bits 7-4 of data buffer Bits 3-0 of data buffer Bits 15-12 of address register Bits 11-8 of address register Bits 7-4 of address register Bits 3-0 of address register Window register Bank register Bits 11-8 of index register Bits 7-4 of memory pointer Memory pointer enable flag Bits 7-4 of index register Bits 3-0 of memory pointer Bits 3-0 of index register Bits 7-4 of register pointer Bits 3-0 of register pointer Program status word BCD flag Compare flag Carry flag Zero flag Index register enable flag Bit 0 of port 0A Bit 1 of port 0A Bit 2 of port 0A Bit 3 of port 0A Bit 0 of port 0B Bit 1 of port 0B Bit 2 of port 0B Bit 3 of port 0B Bit 0 of port 0C Bit 1 of port 0C Bit 2 of port 0C Bit 3 of port 0C Bit 0 of port 0D Bit 1 of port 0D Bit 2 of port 0D Bit 3 of port 0D
54
PD17215, 17216, 17217, 17218
Table 11-2 Reserved Symbols (2/2)
Symbol Name P0E0 P0E1 P0E2 P0E3 SP SYSCK WDTRES BTMCK BTMRES INT NRZBF NRZ P0EBPU0 P0EBPU1 P0EBPU2 P0EBPU3 IEG P0EBIO0 P0EBIO1 P0EBIO2 P0EBIO3 IPBTM IP IPTM TMEN TMRES TMCK1 TMCK0 IRQBTM IRQ IRQTM TMC TMM NRZLTMM NRZHTMM AR Attribute FLG FLG FLG FLG MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG DAT DAT DAT DAT DAT Value 0.6FH.0 0.6FH.1 0.6FH.2 0.6FH.3 0.81H 0.82H.0 0.83H.3 0.83H.2 0.83H.1 0.8FH.0 0.91H.0 0.92H.0 0.97H.0 0.97H.1 0.97H.2 0.97H.3 0.9FH.0 0.0A7H.0 0.0A7H.1 0.0A7H.2 0.0A7H.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 0.0B3H.3 0.0B3H.2 0.0B3H.1 0.0B3H.0 0.0BDH.0 0.0BEH.0 0.0BFH.0 05H 06H 03H 04H 40H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W Bit 0, port 0E Bit 1, port 0E Bit 2, port 0E Bit 3, port 0E Stack pointer Selects system clock Resets watchdog timer Selects basic interval timer mode Resets basic interval timer mode INT pin status NRZ buffer data NRZ data Pull-up resistor setting flag for P0E0 Pull-up resistor setting flag for P0E1 Pull-up resistor setting flag for P0E2 Pull-up resistor setting flag for P0E3 Selects interrupt edge for INT pin I/O setting flag, P0E0 I/O setting flag, P0E1 I/O setting flag, P0E2 I/O setting flag, P0E3 Interrupt enable flag of basic interval timer INT interrupt enable flag 8-bit timer interrupt enable flag 8-bit timer count enable flag 8-bit timer reset flag Selects clock source for 8-bit timer Selects clock source for 8-bit timer Basic interval timer interrupt request flag INT interrupt request flag 8-bit timer interrupt request flag 8-bit counter 8-bit modulo register NRZ low level period setting modulo register NRZ high level period setting modulo register Address register Description
55
PD17215, 17216, 17217, 17218
Fig. 11-1 Register Files (1/2)
Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0
0
1
2
3
4
5
6
7
*
* 0 SP 1 0 0 0 0
*
*
*
*
*
*
0 WDTRES 0 0 BTMCK 0 0 BTMRES 0 0 0
P0EBPU3 0 P0EBPU2 0 P0EBPU1 0 P0EBPU0 0 P0EBIO3 0 P0EBIO2 0 P0EBIO1 0 P0EBIO0 0
1 SYSCK 0 0 0 0 0 0 0 0 0 0 NRZ 0 0 0 0
NRZBF 0
TMEN 1 TMRES 0 TMCK1 0 TMCK0 0
*: On reset
Fig. 11-2 Data Memory Configuration
Column address 7 8 9
0 0 1
1
2
3
4
5
6
A
B
C
D
E
F DBF
DBF3DBF2DBF1DBF0
Row address
2 3 4 5 6 7 P0E0 -P0E3
AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW System register P0D 0 -P0D3 P0C0 -P0C3 P0B 0 -P0B 3 P0A 0 -P0A3
56
PD17215, 17216, 17217, 17218
Fig. 11-1 Register Files (2/2)
Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0
8
9
A
B
C
D
E
F
*
*
*
*
*
*
* 0 0 0 INT 0 0 0 IEG 0
* 0 0 0 P 0 0 0 0 0
IPBTM 0 IP IPTM 0 0 0 0 0 0 0 0 0 IRQ 0 0 0 0 0 0 0 0 0 0 0
IRQBTM 0
0 IRQTM 1
*: On reset P: When INT pin is high level, 1 or when INT pin is low level, 0.
Table 11-3 Peripheral Hardwre
Name TMC TMM NRZLTMM NRZHTMM AR Address 05H 06H 03H 04H 40H Valid Bit 8 8 8 8 16 Description 8-bit timer count register 8-bit timer modulo register Low level period setting modulo register for remote controller carrier generation High level period setting modulo register for remote controller carrier generation Address register
57
PD17215, 17216, 17217, 17218
12. INSTRUCTION SET
12.1 Instruction Set Outline
b15 b14-b11 BIN. 0000 0001 0010 0011 0100 0101 0110 HEX. 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET RETSK EI DI 0111 7 RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP 1000 1001 1010 1011 1100 1101 1110 1111 8 9 A B C D E F LD SKE MOV SKNE BR BR BR BR r, m m, #n4 @r, m m, #n4 addr (Page 0) addr (Page 1) addr (Page 2) addr (Page 3) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n AR AR DBF, p p, DBF WR, rf rf, WR r s h r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1
58
PD17215, 17216, 17217, 17218
12.2 AR ASR addr BANK CMP CY DBF h INTEF INTR INTSK IX MP MPE m mR mC n n4 PAGE PC p pH pL r rf rfR rfC SP s WR (x) Legend : Address register : Address stack register specified by stack pointer : Program memory address (lower 11 bits) : Bank register : Compare register : Carry flag : Data buffer : Halt releasing condition : Interrupt enable flag : Register automatically saved to stack in case of interrupt : Interrupt stack register : Index register : Data memory row address pointer : Memory pointer enable flag : Data memory address specified by mR, mC : Data memory row address (high) : Data memory column address (low) : Bit position (4 bits) : Immediate data (4 bits) : Page (bit 11 and 12 of program counter) : Program counter : Peripheral address : Peripheral address (higher 3 bits) : Peripheral address (lower 4 bits) : General register column address : Register file address : Register file address (higher 3 bits) : Register file address (lower 4 bits) : Stack pointer : Stop releasing condition : Window register : Contents addressed by x
59
PD17215, 17216, 17217, 17218
12.3 List of Instruction Sets
Instruction Code Group Mnemonic Operand Operation OP Code 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 mR mR mR mR mR 000 Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 mC mC mC mC mC 0001 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r r r r r n4 0000
r, m ADD m, #n4 r, m Addition ADDC m, #n4 AR INC IX r, m SUB Subtraction SUBC m, #n4 r, m OR m, #n4 r, m Logical AND m, #n4 r, m XOR m, #n4 SKT Judge SKF SKE SKNE Compare SKGE SKLT Rotate RORC LD ST m, #n4 m, #n4 r r, m m, r @r, m Transfer MOV m, @r m, #n4 MOVT DBF, @AR m, #n m, #n4 m, #n4 m, #n m, #n4 r, m
(r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR +1 IX IX +1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 CMP 0, if (m) CMP 0, if (m)
n = n, then skip n = 0, then skip
11110 11111 01001 01011 11001 11011 00111 01000 11000 01010 11010 11101 00111
(m)-n4, skip if zero (m)-n4, skip if not zero (m)-n4, skip if not borrow (m)-n4, skip if borrow
CY (r)b3 (r)b2 (r)b1 (r)b0
(r) (m) (m) (r) if MPE = 1 : (MP, (r)) (m) if MPE = 0 : (BANK, mR, (r)) (m) if MPE = 1 : (m) (MP, (r)) if MPE = 0 : (m) (BANK, mR, (r)) (m) n4 SP SP - 1, ASR PC, PC AR DBF (PC), PC ASR, SP SP + 1
60
PD17215, 17216, 17217, 17218
Instruction Code Group Mnemonic Operand Operation OP Code 00111 00111 00111 00111 00111 00111 PC10-0 addr PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 0 01100 01100 01101 01100 01101 addr 01110 01100 01101 01110 01111 00111 11100 00111 00111 00111 00111 00111 00111 00111 00111 00111 000 000 001 100 000 001 010 011 100 000 0100 addr 0101 1110 1110 1110 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 s h 0000 0000 000 000 rfR rfR pH pH Operand 1101 1100 0011 0010 1011 1010 0000 0000 rfC rfC pL pL
PUSH POP PEEK Transfer POKE GET PUT
AR AR WR, rf rf, WR DBF, p p, DBF
SP SP - 1, ASR AR AR ASR, SP SP +1 WR (rf) (rf) WR (DBF) (p) (p) (DBF)
PD17215 PD17216
PD17217
Branch BR addr
PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 PC10-0 addr, PAGE 0
PD17218
PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 PC10-0 addr, PAGE 3
@AR addr CALL @AR Subroutine RET RETSK RETI Interrupt EI DI STOP Other HALT NOP s h
PC AR SP SP - 1, ASR PC, PC10-0 addr, PAGE 0 SP SP - 1, ASR PC, PC AR PC ASR, SP SP +1 PC ASR, SP SP +1 and skip PC ASR, INTR INTSK, SP SP +1 INTEF 1 INTEF 0 STOP HALT No operation
61
PD17215, 17216, 17217, 17218
12.4
Assembler (AS17K) Built-In Macro Instruction flag n: FLG type symbol < >: Contents in < > can be omitted Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n) 0 if description = flag n, then (flag n) 1 (BANK) n n 1n4 1n4 1n4 1n4 1n4 1n4 n = 0, 1
Legend
Mnemonic SKTn Built-in macro SKFn SETn CLRn NOTn INITFLG BANKn
Operand flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ***< flag n>
62
PD17215, 17216, 17217, 17218
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Item Supply Voltage Input Voltage Output Voltage Symbol VDD VI VO Peak value REM pin Effective value High-Level Output Current* IOH 1 pin (P0E pin) Effective value Peak value Total of P0E pins Effective value 1 pin (P0C, P0D, P0E, REM or WDOUT pin) Low-Level Output Current* Total of P0C, P0D, WDOUT pins IOL Total of P0E pins Effective value Operating Ambient Temperature Storage Temperature Power Dissipation TA Tstg Pd TA = 85 C 20.0 -40 to +85 -65 to +150 180 mA C C mW Peak value Effective value Peak value Effective value Peak value -15.0 7.5 5.0 22.5 15.0 30.0 mA mA mA mA mA mA -5.0 -22.5 mA mA Peak value -24.0 -7.5 mA mA Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -36.0 Unit V V V mA
*: Calculate effective value by this expression: [Effetive value] = [Peak value] x Duty Caution: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
63
PD17215, 17216, 17217, 17218
Recommended Operating Ranges (VDD = 2.0 to 5.5 V, TA = -40 to +85C)
Item Symbol VDD1 fx = 1 MHz Conditions High-speed mode (Instruction execution time: 16 s) 2.0 VDD2 Supply Voltage VDD3 fx = 4 MHz High-speed mode (Instruction execution time: 4 s) fx = 8 MHz High-speed mode (Instruction execution time: 2 s) 2.2 3.0 5.5 Ordinary mode (Instruction execution time: 8 s) V 3.0 5.5 MIN. TYP. MAX. Unit
VDD4
3.5
5.0
5.5
Oscillation Frequency Operating Temperature Low-Voltage Detector Circuit* (Mask Option)
fx Ta TCY Ta = -10 to +85C
1.0 -40 8
4.0 +25
8.0 +85 32
MHz C
S
*: Reset if the status of VDD = 0.8 to 2.2 V lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected (when the RESET pin and WDOUT pin are connected). Some oscillators stop oscillating before the reset function is effected.
f X vs V DD
(MHz) 10 9 8 7 6 5
System clock: f X (Ordinary mode)
4 3 Operation guaranteed area 2
1
0.4 0 2 2.2 3 3.5 4 5 5.5 6 (V) Supply voltage: V DD
Remark:
The region indicated by the broken line in the above figure is the guaranteed operating range in the high-speed mode.
64
PD17215, 17216, 17217, 17218
System Clock Oscillator Circuit Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V)
Resonator Recommended Constants Item Oscillation frequency (fx)*1 Oscillation stabilization time*2 After VDD reached MIN. in oscillation voltage range Conditions MIN. TYP. MAX. Unit
XIN
XOUT
1.0
4.0
8.0
MHz
Ceramic
4
ms
* 1: The oscillation frequency only indicates the oscillator characteristics. 2: The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution: To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: * Keep wiring length as short as possible. * Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. * Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. * Do not extract signals from the oscillator circuit. External circuit example
XIN
XOUT R1
C3
C2
65
PD17215, 17216, 17217, 17218
Ceramic resonators Recommended Circuit Constants C1 (pF) Murata Mfg, Co., Ltd. CSB1000J CSA2.00MG CSA4.00MG CSA6.00MG CSA8.00MTZ CST2.00MG CST4.00MGW CST6.00MGW CST8.00MTW Kyocela Corp. KBR-1000Y/F KBR-2.0MS KBR-4.0MSA KBR-4.0MKS/MWS KBR-6.0MSA KBR-6.0MKS/MWS KBR-8.0M PBRC2.00A PBRC3.58A PBRC4.00A PBRC6.00A PBRC8.00A TDK Corp. FCR2.0M3 FCR2.0MC3 FCR4.0M5 FCR4.0MC5 CCR4.0MC3 Matsushita Electronics Components Co., Ltd. EFOEC2004A4 EFOEC4004A4 EFOEC6004A4 EFOEC8004A4 EFOEN2004A4 EFOEN4004A4 EFOEN6004A4 EFOEN8004A4 100 30 30 30 30 - - - - 100 47 33 - 33 - 33 47 33 33 33 33 33 - 33 - - - - - - 33 33 33 33 C2 (pF) 100 30 30 30 30 - - - - 100 47 33 - 33 - 33 47 33 33 33 33 33 - 33 - - - - - - 33 33 33 33 R1 (k) 4.7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Oscillation Voltage Range MIN. (V) 2.0 2.0 2.0 2.0 2.1 2.0 2.0 2.0 2.1 2.0 2.0 2.0 2.0 2.2 2.0 2.2 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5
Manufacturer
Product Name
66
PD17215, 17216, 17217, 17218
DC Characteristics (VDD = 2.0 to 5.5 V, TA = -40 to +85C)
Item Symbol VIH1 VIH2 High-Level Input Voltage VIH3 VIH4 VIH5 VIL1 VIL2 Low-Level Input Voltage VIL3 VIL4 High-Level Input Leakage Current ILIH P0E XIN INT, RESET, P0A, P0B, P0E INT P0E VIH = VDD 0 0 0.35VDD 0.2VDD 3.0 V V RESET, INT pin P0A, P0B P0E P0E XIN RESET, INT pin P0A, P0B 2.0 V VDD < 3.0 V 3.0 V VDD 5.5 V Conditions MIN. 0.8VDD 0.7VDD VDD-0.3 VDD-0.5 0.8VDD 0 0 TYP. MAX. VDD VDD VDD VDD VDD 0.2VDD 0.3VDD Unit V V V V V V V
A A A A A A A A
k k k k mA V
ILIL1 Low-Level Input Leakage Current ILIL2
VIL = 0 V VIL = 0 V w/o pull-up resistor VOH = VDD
-3.0 -3.0
High-Level Output Leakage Current
ILOH
P0C, P0D, P0E, WDOUT WDOUT P0E
3.0
ILOL1 Low-Level Output Leakage Current ILOL2
VOL = 0 V VOL = 0 V w/o pull-up resistor VIH = VDD VIL = 0 V VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% VDD = 5 V 10% VOH = 1.0 V, VDD = 3 V IOH = -0.5 V mA IOL = 0.5 mA 25 25 100 100 -6.0 VDD-0.3 50 50 200 200 -13.0
-3.0 -3.0
High-Level Input Current Low-Level Input Current
IIH IIL
XIN XIN RESET, P0E
20 -20 100 100 400 400
RU1 RESET, P0E Internal Pull-Up Resistor P0A, P0B RU2 P0A, P0B High-Level Output Current High-Level Output Voltage IOH VOH VOL1 Low-Level Output Voltage VOL2 Low-Voltage Detector Circuit (Mask Option) VDT1 VDT2 Data Retension Voltage VDDR TA = -10 to +85C STOP mode REM P0E, REM P0C, P0D, REM, WDOUT P0E
0.3
V
IOL = 1.5 mA 0.8 0.8 1.3 1.6 1.6
0.3 2.4 2.2
V V V V
67
PD17215, 17216, 17217, 17218
Item
Symbol IDD1 Operating mode (high-speed mode) HALT mode Operating mode (high-speed mode)
Conditions fx = 8 MHz VDD = 5 V 10% fx = 8 MHz VDD = 5 V 10% VDD = 3 V 10% fx = 4 MHz Operating mode (ordinary mode) VDD = 5 V 10% VDD = 3 V 10% VDD = 2 to 2.2 V VDD = 5 V 10%
MIN.
TYP. 2
MAX. 4
Unit mA
IDD2
0.9 1.3 0.5 1.0 0.4 0.2 0.8 0.3 0.15 0.25 0.15 0.2 0.1 1 1 1 1 1 1 1 1 1
2.4 3.0 1.0 2.0 0.8 0.4 1.8 0.6 0.3 0.5 0.3 0.4 0.2 30 20 16 20 10 8 5 5 5
mA mA mA mA mA mA mA mA mA mA mA mA mA
IDD3
IDD4
HALT mode
fx = 4 MHz
VDD = 3 V 10% VDD = 2 to 2.2 V
Supply Current
IDD5
Operating mode (high-speed mode)
VDD = 3 V 10% fx = 1 MHz VDD = 2 to 2.2 V VDD = 3 V 10%
IDD6
HALT mode
fx = 1 MHz VDD = 2 to 2.2 V VDD = 5 V 10%
A A A A A A A A A
IDD7
STOP mode (TA = -40 to +85C)
VDD = 3 V 10% VDD = 2 to 2.2 V VDD = 5 V 10%
IDD8
STOP mode (TA = -20 to +70C)
VDD = 3 V 10% VDD = 2 to 2.2 V VDD = 5 V 10%
IDD9
STOP mode (TA = 25C)
VDD = 3 V 10% VDD = 2 to 2.2 V
68
PD17215, 17216, 17217, 17218
AC Characteristics (VDD = 2.0 to 5.5 V, TA = -40 to +85C)
Item Symbol tCY1 CPU Clock Cycle Time* (Instruction Execution Time) tCY2 tCY3 INT High/Low Level Width tIOH, tIOL VDD = 4.5 to 5.5 V Conditions VDD = 3.5 to 5.5 V VDD = 2.2 to 5.5 V MIN. 1.99 3.98 7.96 10 50 RESET Low Level Width tRSL VDD = 4.5 to 5.5 V 10 50 TYP. MAX. 32.2 32.2 32.2 Unit
s s s s s s s
*: The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the oscillator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics (refer to 4. CLOCK GENERATOR CIRCUIT).
CPU clock cycle time tCY [ s]
10 9 8 7 6 5 4 3 2 40 32
tCY vs VDD
2.2 0 1 2 3 4 5 6
Supply voltage V DD [V]
69
PD17215, 17216, 17217, 17218
14. CHARACTERISTIC WAVEFORMS (REFERENCE VALUE)
IDD vs VDD (Oscillation at 1 MHz) 3.0 (TA = 25C) 3.0 IDD vs VDD (Oscillation at 4 MHz) (TA = 25C)
Operating supply current IDD (mA)
2.0
Operating supply current IDD (mA)
2.0 High-speed operation mode
Normal operation mode 1.0 HALT mode
1.0
High-speed operation mode Normal operation mode HALT mode
0 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD (V)
0 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD (V)
IDD vs VDD (Oscillation at 8 MHz) 3.0 (TA = 25C)
High-speed operation mode Operating supply current IDD (mA)
2.0 Normal operation mode
HALT mode 1.0
0 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD (V)
70
PD17215, 17216, 17217, 17218
IDD vs fX (Operation mode) 2.2 (TA = 25C)
2.0 High-speed mode 1.8 Normal mode
Operating supply current IDD (mA)
VDD = 5.0 V
1.6
1.4 VDD = 5.0 V 1.2
1.0 VDD = 3.0 V 0.8
0.6
VDD = 3.0 V
0.4
0.2
0 0 1 4 8 fX (MHZ)
IDD vs fX (HALT mode) 1.2 (TA = 25C)
1.0 VDD = 5.0 V
HALT current IDD (mA)
0.8
0.6
0.4 VDD = 3.0 V 0.2 VDD = 2.0 V
0
0
1
4
8
fX (MHZ)
71
PD17215, 17216, 17217, 17218
IOH (REM) vs VDD-VOH (TA = 25C) -40 -40
IOH (P0E) vs VDD-VOH (TA = 25C)
VDD = 5.0 V VDD = 5.0 V High-level output current IOH (REM) (mA) High-level output current IOH (P0E) (mA)
-30
-30
-20
-20
VDD = 3.0 V
VDD = 3.0 V -10
-10
VDD = 2.0 V
VDD = 2.0 V
0 0 1 2 3 4 5 VDD-VOH (V)
0 0 1 2 3 4 5 VDD-VOH (V)
IOL (REM/P0C/P0D) vs VOL (TA = 25C) 40 40
IOL (P0E) vs VOL (TA = 25C)
Low-level output current IOL (REM/P0C/P0D) (mA)
Low-level output current IOL (P0E) (mA)
VDD = 5.0 V 30
VDD = 5.0 V 30
VDD = 3.0 V
20
20
VDD = 2.0 V
VDD = 3.0 V 10
10
VDD = 2.0 V
0 0 1 2 3 4 5
0 0 1 2 3 4 5 Low-level output voltage VOL (V) Low-level output voltage VOL (V)
72
PD17215, 17216, 17217, 17218
15. APPLICATION CIRCUIT EXAMPLE
P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM 3V VDD XOUT 4 MHz XIN GND RESET WDOUT
1 2 3 4 5
28 27 26 25 24
P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0
PD17215CT/GT- xxx PD17216CT/GT- xxx PD17217CT/GT- xxx PD17218CT/GT- xxx
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
Remark:
The RESET pin can be connected to a pull-up resistor by the mask option.
73
PD17215, 17216, 17217, 17218
16. PACKAGE DRAWINGS
28 PIN PLASTIC SHRINK DIP (400 mil)
28 15
1 A
14
K
I
L
J
G
H
F D N
M
C
B
M
R
NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R MILLIMETERS 28.46 MAX. 2.67 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 -0.05 0.17 0~15 INCHES 1.121 MAX. 0.106 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.400 (T.P.) 0.339 0.010 +0.004 -0.003 0.007 0~15 S28C-70-400B-1
74
PD17215, 17216, 17217, 17218
28 PIN PLASTIC SOP (375 mil)
28 15
detail of lead end
1 A
14
P
H I
F
G
J
E
K
C D
NOTE
B M
M
L N
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 18.07 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 2.9 MAX. 2.50 10.30.3 7.2 1.6 0.15 +0.10 -0.05 0.80.2 0.12 0.15 3 +7 -3
INCHES 0.712 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.115 MAX. 0.098 0.406 +0.012 -0.013 0.283 0.063 0.006 +0.004 -0.002 0.031 +0.009 -0.008 0.005 0.006 3 +7 -3 P28GM-50-375B-3
Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
75
PD17215, 17216, 17217, 17218
17. RECOMMENDED SOLDERING CONDITIONS
For the PD17215, 17216, 17217, and 17218, soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor device mounting technology manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 17-1 Soldering Conditions of Surface Mount Tye
PD17215GT-xxx: PD17216GT-xxx: PD17217GT-xxx: PD17218GT-xxx:
Soldering Method Infrated Reflow
28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil) 28-pin plastic SOP (375 mil)
Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max., Days: 7 days* (after that, prebaking is necessary for 20 hours at 125 C) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Package peak temperature: 215 C, Time: 40 seconds max. (210 C min.), Number of times: 2 max., Days: 7 days* (after that, prebaking is necessary for 20 hours at 125 C) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) Symbol IR35-207-2
VPS
VP15-207-2
Partial Heating
--
*: The number of days the device can be stored after the dry pack was opened, under storage conditions of 25 C and 65 % RH max.
Caution: Do not use two or more solderong methods in combination (except the partial heating method). Table 17-2 Soldering Conditions of Through-Hole Tye
PD17215CT-xxx: PD17216CT-xxx: PD17217CT-xxx: PD17218CT-xxx:
Soldering Method Wave Soldering (Only for pins) Partial Heating
28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil)
Soldering Conditions Solder bath temperature: 260 C max., Time: 10 seconds max. Pin temperature: 300 C max., Time: 3 seconds max. (per pin)
Caution:
The wave solding must be performed at the lead part only. Note that the solder must not be directly contacted to the package body.
76
PD17215, 17216, 17217, 17218
APPENDIX A. DIFFERENCES AMONG PD17215, 17216, 17217, 17218 AND PD17P218
PD17P218 is equipped with PROM to which data can be written by the user instead of the internal mask ROM
(program memory) of the PD17218. Table A-1 shows the differences between the PD17215, 17216, 17217, 17218 and PD17P218. The differences among these five models are the program memory and mask option, and their CPU functions and internal hardware are identical. Therefore, the PD17P218 can be used to evaluate the program developed for the
PD17215, 17216, 17217, and 17218 system. Note, however, that some of the electrical specifications such as
supply current and low-voltage detection voltage of the PD17P218 are different from those of the PD17215, 17216, 17217, and 17218. Table A-1 Differences among PD17215, 17216, 17217, 17218 and PD17P218
Product Name Item
PD17P218
One-time PROM
PD17215
PD17216
PD17217
PD17218
Mask ROM
Program Memory
16 K bytes (8192 x 16) 4 K bytes (2048 x 16) 8 K bytes (4096 x 16) 12 K bytes (6144 x 16) 16 K bytes (8192 x 16) (0000H-1FFFH) (0000H-07FFH) (0000H-0FFFH) (0000H-17FFH) (0000H-1FFFH)
Data Memory Pull-Up Resistor of RESET Pin Low-Voltage Detector Circuit * VPP Pin, Operation Mode Select Pin
223 x 4 bits Provided Provided Provided
111 x 4 bits Any (mask option) Any (mask option) Not provided
223 x 4 bits
Instruction Execution Time
2 s (8 MHz ceramic oscillator: in high-speed mode) 4 s (4 MHz ceramic oscillator: in high-speed mode) 16 s (1 MHz ceramic oscillator: in high-speed mode) Retain output level immediately before standby mode VDD = 2.2 to 5.5 V (at fX = 4 MHz, in high-speed mode) 28-pin plastic SOP (375 mil) 28-pin plastic shrink DIP (400 mil)
Operation When P0C, P0D Are Standby Supply Voltage Package
*: Although the circuit configuration is identical, its electrical characterisitcs differ depending on the product.
77
PD17215, 17216, 17217, 17218
APPENDIX B. FUNCTIONAL COMPARISON OF PD17215 SUBSERIES RELATED PRODUCTS
PD17201A
3072 x 16
Product Name Item ROM Capacity (Bit) RAM Capacity (Bit) LCD Controller/Driver
PD17207
4096 x 16
PD17202A
PD17215
PD17216
4096 x 16
PD17217
6144 x 16
PD17218
8192 x 16
2048 x 16 112 x 4 96 segments max. LED output is lowactives 16 lines
336 x 4 136 segments max.
111 x 4 Not provided
223 x 4
Infrared Remote Controller Carrier Generator (REM) I/O Ports External Interrupt (INT) Analog Input Timer Watchdog Timer Low-Voltage Detector Circuit* Serial Interface Stack
LED output is high-actives 19 lines 1 line (rising-edge detection) 4-channels (8-bit A/D) 2-channels

Internal (no LED output)
20 lines 1 line (rising-edge, falling-edge, detection) Not provided 2-channels

8-bit timer Watch timer
8-bit timer Basic interval timer
Internal (WDOUT output) Not provided 1-channel Internal (WDOUT output) Not provided 5 levels (3 levels for multiplexed interrupt) 4 s (4 MHz: with ceramic or crystal oscillator) * 2 s (8 MHz ceramic oscillator: In high-speed mode) * 4 s (4 MHz ceramic oscillator: In high-speed mode) * 16 s (1 MHz ceramic oscillator: In high-speed mode) Not provided
Instruction Execution Time
Main System Clock
Subsystem Clock Supply Voltage (With Subsystem Clock) Standby Function Package One-Time PROM Products
488 ms (32.768 kHz: with crystall oscillator) VDD = 2.2 to 5.5 V (VDD = 2.0 to 5.5 V)
VDD = 2.2 to 5.5 V STOP, HALT
80-pin plastic QFP
64-pin plastic QFP
28-pin plastic SOP 28-pin plastic shrink DIP
PD17P207
PD17P202A
PD17P218
*: Note that although all the prodcts have the same circuit construction, the electrical specifications differ dependant on each product.
78
PD17215, 17216, 17217, 17218
APPENDIX C. DEVELOPMENT TOOLS
To develop the programs for the PD17215 subseries, the following development tools are available: Hardware
Name Remarks IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators used in common with the 17K series microcomputer. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM as the host machine with RS-232C. EMU-17K is inserted into the expansion slot of a PC-9800 series. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOST TM. EMU-17K also has a function by which you can check the contents of data memory real-time. This is an SE board for PD17215 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K28CT is an emulation probe for 17K series 28-pin shrink DIP (400mil).
In-Circuit Emulator IE-17K, IE-17K-ET *1, EMU-17K *2
SE Board (SE-17215) Emulation Probe (EP-17K28CT) Emulation Probe (EP-17K28GT) Conversion Adapter (EV-9500GT-28 *3) PROM Programmer (AF-9703 *4, AF-9704 *4, AF-9705 *4 , AF-9706 *4) Program Adapter (AF-9808J *4, AF-9808H *4)
EP-17K28GT is an emulation probe for 17K series 28-pin SOP (375 mil). When used with EV-9500GT-28 Note 3, it connects an SE board to the target system. EV-9500GT-28 is a conversion adapter for 28-pin SOP (375 mil) and is used to connect EP-17K28GT to the target system. AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to PD17P218. By connecting program adapter AF-9808J or AF-9808H to this PROM programmer, PD17P218 can be programmed. AF-9808J and AF-9808H are adapters that is used to program PD17P218CT and PD17P218GT respectively, and is used in combination with AF-9703, AF-9704, AF-9705, or AF-9706.
*1: Low-cost model: External power supply type 2: This is a product from I.C Corp. For details, consult I.C Corp. (Tel: Tokyo 03-3447-3793). 3: Two EV-9500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are optionally available as a set. 4: These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: Tokyo 033733-1163).
79
PD17215, 17216, 17217, 17218
Software
Name Outline Host Machine OS Media Supply 5" 2HD PC-9800 series MS-DOSTM 3.5" 2HD Order Code
17K Series Assembler (AS17K)
AS17K is an assembler common to the 17K series products. When developing the program of the PD17215 subseries, AS17K is used in combination with a device file (AS17215, AS17216, AS17217, or AS17218).
S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K
S5A10AS17215 * S5A10AS17215 * S5A10AS17215 * S5A10AS17215 *
5" 2HC IBM PC/AT PC DOSTM 3.5" 2HC
Device File AS17215 AS17216 AS17217 AS17218
AS17215, AS17216, AS17217, and AS17218 are device files for PD17215, 17216, 17217, and 17218 respectirely, and are used in combination with an assembler for the 17K series (AS17K).
5" 2HD PC-9800 series MS-DOS 3.5" 2HD
5" 2HC IBM PC/AT PC DOS 3.5" 2HC
Support Software (SIMPLEHOST)
SIMPLEHOST is a software package that enables manmachine interface on the TM Windows when a program is developed by using an in-circuit emulator and a personal computer.
5" 2HD PC-9800 series MS-DOS 3.5" 2HD Windows 5" 2HC IBM PC/AT PC DOS 3.5" 2HC
S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K
*: SxxxxAS17215 includes AS17215, AS17216, AS17217, and AS17218. Remark: The corresponding OS versions are as follows:
OS MS-DOS PC DOS Windows Ver. 3.30 to Ver. 5.00A * Ver. 3.1 to Ver. 5.0 * Ver. 3.0 to Ver. 3.1 Version
*: Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software.
80
PD17215, 17216, 17217, 17218
[MEMO]
81
PD17215, 17216, 17217, 17218
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. circuitry. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
82
PD17215, 17216, 17217, 17218
83
PD17215, 17216, 17217, 17218
SIMPLEHOST is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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